Question

Consider a non-pipeline processor with 2 GHz clock, average CPI of '6'. It is hence with a 5-stage pipeline processor with the same clock, consider 1 instructions per cycle and if 20% instructions have 2 cycle stalls due to control hazards and 20% of instructions have 3 cycles stalls due to data hazards. Speedup of pipeline over non-pipeline

Answer 1

The correct answer is 3 times.