Question:

If the converter of Dual-slope ADC first integrates the analog input signal for a fixed duration, then the clock periods are

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In dual-slope ADCs, the integration interval is generally chosen as \(2^n\) clock cycles to achieve \(n\)-bit resolution.
Updated On: Jun 25, 2026
  • \(n\)
  • \(n-1\)
  • \(2^n\)
  • \(2^{n-1}\)
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The Correct Option is C

Solution and Explanation

Concept: A dual-slope ADC operates in two phases:
• Integration of the unknown input voltage.
• De-integration using a reference voltage. For an \(n\)-bit dual-slope ADC, the fixed integration interval is selected as \[ 2^n \] clock periods.

Step 1:
Recall dual-slope ADC operation.
The unknown voltage is integrated for a fixed time. This fixed time corresponds to \[ 2^n \] clock pulses.

Step 2:
State the result.
Therefore, \[ \boxed{2^n} \] clock periods are used.
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