List of top Computer Awareness Questions on Computer Architecture asked in NIMCET

Fetch - Decode - Execute cycle of CPU is called?
In standard machine language instruction which component identifies the specific operation to be performed such as addition or data movement:
Which about fetch decode execute cycle in CPU are correct? I. Program counter is incremented after each instruction is fetched so the CPU move to the next instruction. II. The Control Unit is responsible for fetching instruction and placing them in the instruction register. III. The ALU is responsible for decoding instruction and determining which operation to perform. IV. Register are used to permanently store operating system's files for fast access.
Consider a system running under two types of workloads: (a) CPU-intensive jobs, (b) I/O-intensive jobs. Which of the following statements about the relative performance of Interrupt-driven I/O and Programmed I/O is correct?

In the design of a control unit of a processor, two common approaches are used: hardware control and microprogrammed control. Consider the following statements: 

I. Hardware control units are generally faster but more difficult to modify than microprogrammed control units. 
II. In a horizontal microprogrammed control unit, each control signal has a separate bit in the control word. 
III. Vertical microprogramming leads to longer control words but provides greater parallelism. 
IV. Microprogrammed control units are typically easier to implement and modify than hardware control units.

In computer architecture, which of the following correctly matches the fundamental unit used in the CPU, cache, and main memory respectively?
Consider a system with a CPU having 6 registers and 32-bit instructions. The maximum possible size of the main memory is 512 KB (1K = 2^{10}). Each instruction takes two registers and one memory address as operands. Which one of the following correctly gives the maximum possible distinct instructions that can be there in the instruction set of the CPU?
In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are:
Which of the following interfaces perform the transfer of data between the memory and the I/O peripheral without involving the CPU?
Which of the following components is used to establish a communication link between a CPU and the peripheral devices to transfer data?
Which of the following components is not a part of an instruction format in CPU processing?
Which of the following do not affect CPU performance?
Cache memory functions as an intermediary between
Consider the following 4-bit binary numbers represented in the 2's complement form: 1101 and 0100. What would be the result when we add them?
Which of the following is true about Von Neumann architecture?
The time required for fetching and execution of one machine instruction is
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
If a processor clock is rated as 2500 million cycles per second, then its clock period is
Which of the following registers is used to keep track of address of memory location where the next instruction is located?
The time required for fetching and execution of one machine instruction is
If a processor clock is rated as 2500 million cycles per second, then its clock period is
Which of the following registers is used to keep track of address of memory location where the next instruction is located?
If a processor clock is rated as 2500 million cycles per second, then its clock period is: