In the circuit shown below, $V_1$ and $V_2$ are bias voltages. Based on input and output impedances, the circuit behaves as a
The $\dfrac{V_{OUT}}{V_{IN}}$ of the circuit shown below is _____________
The h-parameters of a two port network are shown below. The condition for the maximum small signal voltage gain $\dfrac{V_{out}}{V_s}$ is _____________
In the circuit below, the voltage $V_L$ is ___________ V (rounded off to two decimal places).
In the circuit below, the voltage $V_L$ is ______________ V (rounded off to two decimal places).}
A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1 $\mu$s. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ____________ $\mu$s (rounded off to two decimal places).
