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Computer Organization and Architecture

Interrupts - Vectored, Non-vectored an...

Exams

GATE CS

Years

2026

Subjects

Computer Organization and Architecture

Topics

Interrupts - Vectored, Non-vectored and Daisy Chaining
Address Space
Cache Memory
Cache Memory - Direct Mapped and Set Associative Mapping
Cache Memory and Virtual Memory
Data-Path and Control Unit
Four Segment Instruction Pipeline
Implied Mode
Indexed Address
Instruction Set Architecture: Load-Store (RISC) Design
Machine Instructions and Addressing Modes
Memory Management
Memory hierarchy
Number Representation - Sign-Magnitude Arithmetic and Overflow
Paging
Pipelining Hazards
Structural Hazards

List of top Computer Organization and Architecture Questions on Interrupts - Vectored, Non-vectored and Daisy Chaining asked in GATE CS

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2?

GATE CS - 2026
GATE CS
Computer Organization and Architecture
Interrupts - Vectored, Non-vectored and Daisy Chaining