>GATE CS
>Computer Organization and Architecture

Found 1 QuestionSET DEFAULT

Selected Filters

Computer Organization and Architecture

Cache Memory and Virtual Memory

Exams

GATE CS

Years

2026

Subjects

Computer Organization and Architecture

Topics

Cache Memory and Virtual Memory
Address Space
Cache Memory
Cache Memory - Direct Mapped and Set Associative Mapping
Data-Path and Control Unit
Four Segment Instruction Pipeline
Implied Mode
Indexed Address
Instruction Set Architecture: Load-Store (RISC) Design
Interrupts - Vectored, Non-vectored and Daisy Chaining
Machine Instructions and Addressing Modes
Memory Management
Memory hierarchy
Number Representation - Sign-Magnitude Arithmetic and Overflow
Paging
Pipelining Hazards
Structural Hazards

List of top Computer Organization and Architecture Questions on Cache Memory and Virtual Memory asked in GATE CS

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.
For a given memory reference, which of the following sequences of events can NEVER happen?

GATE CS - 2026
GATE CS
Computer Organization and Architecture
Cache Memory and Virtual Memory