List of top Computer Organization and Architecture Questions on Memory hierarchy asked in GATE CS

A disk of size 512M bytes is divided into blocks of 64K bytes. A file is stored in the disk using linked allocation. In linked allocation, each data block reserves 4 bytes to store the pointer to the next data block. The link part of the last data block contains a NULL pointer (also of 4 bytes). Suppose a file of 1M bytes needs to be stored in the disk. Assume, 1K = \(2^{10}\) and 1M = \(2^{20}\). The amount of space in bytes that will be wasted due to internal fragmentation is ___________. (Answer in integer)

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is __________. (rounded off to two decimal places)
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In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows: The OS correctly predicts only up to next 4 page references (including the current page) at the time of allocating a frame to a page. A process accesses the pages in the following order of page numbers: 1, 3, 2, 4, 2, 3, 1, 2, 4, 3, 1, 4. If the system has three memory frames that are initially empty, the number of page faults that will occur during execution of the process is __________. (Answer in integer)

A disk of size 512M bytes is divided into blocks of 64K bytes. A file is stored in the disk using linked allocation. In linked allocation, each data block reserves 4 bytes to store the pointer to the next data block. The link part of the last data block contains a NULL pointer (also of 4 bytes). Suppose a file of 1M bytes needs to be stored in the disk. Assume, 1K = \(2^{10}\) and 1M = \(2^{20}\). The amount of space in bytes that will be wasted due to internal fragmentation is ___________. (Answer in integer)

Refer to the given 3-address code sequence. This code sequence is split into basic blocks. The number of basic blocks is __________. (Answer in integer)
1001: i = 1
1002: j = 1
1003: t1 = 10i
1004: t2 = t1+j
1005: t3 = 8t2
1006: t4 = t3-88
1007: a[t4] = 0.0
1008: j = j+1
1009: if j <= 10 goto 1003
1010: i = i+1
1011: if i <= 10 goto 1002
1012: i = 1
1013: t5 = i-1
1014: t6 = 88t5
1015: a[t6] = 1.0
1016: i = i+1
1017: if i <= 10 goto 1013

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If the data is not found in L1 cache, it goes to L2 cache. If it fails to get the data from L2 cache, it goes to main memory, where the data is definitely available. Hit rates and access times of various memory units are shown in the figure. The average memory access time in nanoseconds (ns) is __________. (rounded off to two decimal places)

In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows: The OS correctly predicts only up to next 4 page references (including the current page) at the time of allocating a frame to a page. A process accesses the pages in the following order of page numbers: 1, 3, 2, 4, 2, 3, 1, 2, 4, 3, 1, 4. If the system has three memory frames that are initially empty, the number of page faults that will occur during execution of the process is \_\_\_\_\_\_\_\_. (Answer in integer)

Consider the following operations on an initially empty stack:
Push 10
Push 20
Pop
Push 30
Pop
Push 40

What is the final content of the stack?

Which of the following is true about the binary search algorithm when applied to a sorted array?

Given a pipeline with 5 stages, the delay for each stage is as follows:

\[ \begin{array}{|c|c|} \hline \textbf{Stage} & \textbf{Delay (ns)} \\ \hline 1 & 250 \\ 2 & 150 \\ 3 & 100 \\ 4 & 200 \\ 5 & 50 \\ \hline \end{array} \]

The buffer delay is 10 ns. Find the time for \( n = 1000 \) instructions.

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

A cache memory that has a hit rate of 0.8 has an access latency of 10 ns and a miss penalty of 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is \(\underline{\hspace{1cm}}\).

Consider a system with 2 KB direct-mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

Consider a set-associative cache of size 2KB with cache block size of 64 bytes. If the width of the tag field is 22 bits, the associativity of the cache is \(\underline{\hspace{2cm}}\).

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements:
\[ S_1:\ \text{Read misses in a write-through L1 cache do not result in writebacks of dirty lines to the L2.} \] \[ S_2:\ \text{Write allocate policy must be used in conjunction with write-through caches and no-write allocate policy is used with writeback caches.} \] Which of the following statements is correct?

Consider a computer system with a byte-addressable primary memory of size \(2^{32}\) bytes.
Assume a direct-mapped cache of size 32 KB and cache block size of 64 bytes. The size of the tag field is \(\underline{\hspace{2cm}}\) bits.