List of top Computer Organization and Architecture Questions on Indexed Address asked in GATE CS

Let \(Z_n\) be the group of integers \(\{0, 1, 2, \dots, n - 1\}\) with addition modulo \(n\) as the group operation. The number of elements in the group \(Z_2 \times Z_3 \times Z_4\) that are their own inverses is ............
A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program \(P\). The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program \(P\), 20\% instructions incur an average of 2 cycles stall due to data hazards and 20\% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ............
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below. R-type Instruction Format: \begin{center} \setlength{\tabcolsep}{15pt} % Adjust column spacing \renewcommand{\arraystretch}{1.5} % Adjust row spacing \begin{tabular}{|c|c|c|c|c|} \hline OPCODE & UNUSED & DST Register & SRC Register1 & SRC Register2
\hline \end{tabular} \end{center} \vspace{0.5cm} I-type Instruction Format: \begin{center} \setlength{\tabcolsep}{15pt} % Adjust column spacing \renewcommand{\arraystretch}{1.5} % Adjust row spacing \begin{tabular}{|c|c|c|c|} \hline OPCODE & DST Register & SRC Register & \# Immediate Value/Address
\hline \end{tabular} \end{center} In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions, and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size. Let \(X\) be the number of bits used to encode the UNUSED field, \(Y\) be the number of bits used to encode the OPCODE field, and \(Z\) be the number of bits used to encode the immediate value/address field. The value of \(X + 2Y + Z\) is ............
A processor with 16 general-purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ............
Which of the following statements is/are FALSE?}
Node X has a TCP connection open to node Y. The packets from X to Y go through an intermediate IP router R. Ethernet switch S is the first switch on the network path between X and R. Consider a packet sent from X to Y over this connection. Which of the following statements is/are TRUE about the destination IP and MAC addresses on this packet at the time it leaves X?
Let \( T(n) \) be the recurrence relation defined as follows: \[ T(0) = 1, \quad T(1) = 2, \quad T(n) = 5T(n-1) - 6T(n-2) \quad \text{for } n \geq 2 \] Which one of the following statements is TRUE?