The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let \(t_{EX}\) denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of \(t_{EX}\) and \(M\) (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below.
The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.
| Instruction | \(t_{EX}\) in nanoseconds | \(M\) |
|---|
| LOAD | 1.8 | 15 |
| IMUL | 1.5 | 10 |
| IDIV | 2.5 | 5 |
| FADD | 1.7 | 10 |
| FSUB | 1.7 | 5 |
| FMUL | 2.8 | 15 |
| FDIV | 3.2 | 5 |
| All other instructions | Less than 1.0 | 35 |
When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)