List of top Analog and Digital Electronics Questions on Combinational Logic Circuits asked in GATE BM

The figure below shows the Karnaugh map (K-map) for a truth table with 4 variables \(A\), \(B\), \(C\) and \(D\). Which one of the following expressions represents the minimum sum of products? Note: The empty cells in the K-map are 0's.

AB / CD	00	01	11	10
00
01		1	1	1
11	1		1	1
10				1

In the following digital circuit, the delay of both the NAND gates is 4 nanoseconds (ns) and the delay of the NOT gate is 1 ns. If a 10 MHz clock signal with 50% duty cycle is given as the input, the duty cycle of the output is %.
(Answer in integer)

In the circuit diagram shown below, the logic gates operate with a supply voltage of 1 V. NAND and XNOR have 200 ps and 400 ps input-to-output delay, respectively.
At time \( t = T \), \( A(t) = 0 \), \( B(t) = 1 \) and \( Z(t) = 0 \). When the inputs are changed to \( A(t) = 1 \), \( B(t) = 0 \) at \( t = 2T \), a 1 V pulse is observed at \( Z \). The pulse width of the 1 V pulse is _________ ps.

Input bits X and Y are added by using the combinational logic as shown below. S represents the sum of the two bits. For a correct implementation of the sum, the signals \(D_0, D_1, D_2, D_3\) are _________, respectively.