List of top Computer Science & Information Technology Questions on Computer Organization and Architecture

A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

Consider $Z = X - Y$, where $X$, $Y$ and $Z$ are all in sign-magnitude form. $X$ and $Y$ are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would require a minimum of:

Von Neumann computers belong to which one of the following classes of computers?

Which one of the following derivations does a top-down parser use while parsing an input string? The input is assumed to be scanned from left to right.

Which one of the following is an important advantage of the DMA mode of data transfer over programmed data transfer?

What is the unit of transfer data from main memory to cache memory?

Which type of I/O does NOT use interrupts?

In disk organization, the time taken by the head to reach the beginning of sector is

Which RAID level describes block interleaved distributed parity?

Which addressing mode allows to directly include operands in an instruction?

Which set of the following instructions is used for program control?

Which register contains the data to be written into memory?

Which phase of the instruction cycle analyzes the instruction to determine type of operation to be performed?

Which bus is used to support local disk drives and peripherals?

The main memory of the system consists of 16 MB, the cache memory can hold 64 KB and data is transferred in blocks of 4 bytes each. What is the tag size in main memory address for direct mapping cache?