List of top Computer Science & Information Technology Questions on Digital Logic asked in AP PGECET

In a 4-bit ripple carry adder, the worst-case delay occurs when _______.
Which of these flip-flops cannot be used to construct a serial shift register?
The output of a JK flip-flop for inputs \( J=1, K=1 \) and clock transition from 1 to 0 is _______.
Assuming 5-bit addition is done on registers, the sum \( 12 + 7 \) leads to _______.